Exemplary embodiments of the present invention relate to a semiconductor memory device, and more particularly, to a global line sharing circuit which can reduce the number of global lines provided in a peripheral region of the semiconductor memory device, thereby reducing a layout area thereof.
Semiconductor memory devices are used in various fields. In particular, semiconductor memory devices are used to store various data. Since such semiconductor memory devices are used in various portable devices, including desktop computers and notebook computers, they are desired to have features of high capacity, high speed operation, small size, and low power consumption.
A semiconductor memory device used for this purpose includes a bank region (CORE) in which cell transistors are provided to record and store data, and a peripheral region (PERI) in which control circuits are provided to control data record of the bank region.
As illustrated in FIG. 1, the peripheral region of the semiconductor memory device includes an AC peripheral region for receiving and controlling a command/address, and a DQ peripheral region for inputting or outputting data.
The peripheral region includes global lines for transferring data of the bank inputted/outputted through data pads (DQ). In addition, the peripheral region includes power planes and signal lines for transferring various control signals and test mode signals.
FIG. 1 illustrates an exemplary structure for executing a test function of a conventional semiconductor memory device.
A test mode signal is for a special function which is used to adjust a timing margin within a semiconductor memory device, change a circuit operation or a control method, or analyze several defects.
Therefore, as many kinds of the test mode signals are used, time taken to analyze defects of the semiconductor memory device is reduced. However, since global lines are provided for the test mode signals within the peripheral region, the increase of the lines causes the increase in the area of the peripheral region.
FIG. 2 illustrates another exemplary structure for executing a test function of a conventional semiconductor memory device.
Referring to FIG. 2, test mode signals the number of which is smaller than the number of test modes are provided and decoded by a test mode decoding circuit, and the decoded test mode signals are used and inputted to a test mode circuit for test purposes.
Test mode code signals TCM(#) are provided in order to use the test mode decoding circuit, and a signal TMGRP is further provided in order to latch the decoded signals. A plurality of signals TMGRP may be provided according to types of test modes.
FIG. 3 illustrates a structure for executing a ZQ calibration function of a conventional semiconductor memory device.
The ZQ calibration is a function which calibrates/adjusts an impedance of a DQ output driver by using a reference resistor (that is, a resistor at node ZQ which can be, e.g., 240 ohms) provided at the outside of the semiconductor memory device. The ZQ calibration circuit is provided within the AC peripheral region of FIG. 3, and the ZQ calibration operation is performed for a certain period of time in response to a ZQ command in an idle state in which the semiconductor memory device does not perform a read/write operation. The ZQ calibration result may be stored in a register as an N-bit digital code. The stored result is inputted to a DQ circuit within the DQ peripheral region and controls an impedance of a DQ output driver.
A plurality of global lines for transferring the test mode signals and the ZQ calibration code signals are provided within the peripheral region. The increase of the global lines causes the increase in the circuit area of the peripheral region.